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8 7 6 1 3 shield 5 2 4 **v dd1 v i * gnd 1 v dd2 ** v o gnd 2 v i , input led1 h l off on truth table (positive logic) nc* i o led1 v o , output h l 40 ns propagation delay, cmos optocoupler technical data hcpl-7710 hcpl-0710 functional diagram *pin 3 is the anode of the internal led and must be left unconnected for guaranteed data sheet performance. pin 7 is not connected internally. **a 0.1 m f bypass capacitor must be connected between pins 1 and 4, and 5 and 8. caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. features ? +5 v cmos compatibility ? 8 ns max. pulse width distortion ? 20 ns max. prop. delay skew ? high speed: 12 mbd ? 40 ns max. prop. delay ? 10 kv/ m s minimum common mode rejection ? C40 to 100 c temp. range ? safety and regulatory approvals ul recognized 2500 v rms for 1 min. per ul 1577 for hcpl-0710 3750 v rms for 1 min. per ul 1577 for hcpl-7710 csa component acceptance notice #5 vde 0884 approved (vde) C v iorm = 630 vpeak for hcpl-7710 option 060 vde 0884 (tuv) C v iorm = 560 vpeak for hcpl-0710 option 060 applications ? digital fieldbus isolation: devicenet, sds, profibus ? ac plasma display panel level shifting ? multiplexed data transmission ? computer peripheral interface ? microprocessor system interface description available in either an 8-pin dip or so-8 package style respectively, the hcpl-7710 or hcpl-0710 optocouplers utilize the latest cmos ic technology to achieve outstanding performance with very low power consumption. the hcpl-x710 require only two bypass capacitors for complete cmos compatibility. basic building blocks of the hcpl-x710 are a cmos led driver ic, a high speed led and a cmos detector ic. a cmos logic input signal controls the led driver ic which supplies current to the led. the detector ic incorporates an integrated photodiode, a high-speed transimpedance amplifier, and a voltage comparator with an output driver.
2 ordering information specify part number followed by option number (if desired) example hcpl-7710#xxx 060 = vde0884 option. 300 = gull wing surface mount option (hcpl-7710 only). 500 = tape and reel packaging option. no option and option 300 contain 50 units (hcpl-7710), 100 units (hcpl-0710) per tube. option 500 contain 1000 units (hcpl-7710), 1500 units (hcpl-0710) per reel. option data sheets available. contact agilent sales representative or authorized distributor. package outline drawing hcpl-7710 8-pin dip package selection guide 8-pin dip small outline (300 mil) so-8 hcpl-7710 hcpl-0710 9.65 ?0.25 (0.380 ?0.010) 1.78 (0.070) max. 1.19 (0.047) max. a xxxxv yyww date code 1.080 ?0.320 (0.043 ?0.013) 2.54 ?0.25 (0.100 ?0.010) 0.51 (0.020) min. 0.65 (0.025) max. 4.70 (0.185) max. 2.92 (0.115) min. dimensions in millimeters and (inches). 5 6 7 8 4 3 2 1 5?typ. 0.254 + 0.076 - 0.051 (0.010 + 0.003) - 0.002) 7.62 ?0.25 (0.300 ?0.010) 6.35 ?0.25 (0.250 ?0.010) type number *option 300 and 500 not marked. option 060 code*
3 package outline drawing hcpl-7710 package with gull wing surface mount option 300 package outline drawing hcpl-0710 outline drawing (small outline so-8 package) 0.635 ?0.25 (0.025 ?0.010) 12?nom. 9.65 ?0.25 (0.380 ?0.010) 0.635 ?0.130 (0.025 ?0.005) 7.62 ?0.25 (0.300 ?0.010) 5 6 7 8 4 3 2 1 9.65 ?0.25 (0.380 ?0.010) 6.350 ?0.25 (0.250 ?0.010) 1.016 (0.040) 1.194 (0.047) 1.194 (0.047) 1.778 (0.070) 9.398 (0.370) 9.906 (0.390) 4.826 (0.190) typ. 0.381 (0.015) 0.635 (0.025) pad location (for reference only) 1.080 ?0.320 (0.043 ?0.013) 4.19 (0.165) max. 1.780 (0.070) max. 1.19 (0.047) max. 2.54 (0.100) bsc dimensions in millimeters (inches). lead coplanarity = 0.10 mm (0.004 inches). 0.254 + 0.076 - 0.051 (0.010 + 0.003) - 0.002) 710v yww 87 65 4 3 2 1 pin one 7 5.842 ?0.203 (0.236 ?0.008) 3.937 ?0.127 (0.155 ?0.005) 0.381 ?0.076 (0.016 ?0.003) 1.270 (0.050) bsg 5.080 ?0.005 (0.200 ?0.005) 3.175 ?0.127 (0.125 ?0.005) 1.524 (0.060) 45?x 0.432 (0.017) 0.228 ?0.025 (0.009 ?0.001) 0.152 ?0.051 (0.006 ?0.002) type number (last 3 digits) date code dimensions in millimeters and (inches). lead coplanarity = 0.10 mm (0.004 inches). *option 500 not marked. 0.305 (0.012) min. option 060 code*
4 all agilent data sheets report the creepage and clearance inherent to the optocoupler component itself. these dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. however, once mounted on a printed circuit board, minimum creepage and clearance requirements must be met as specified for individual equipment standards. for creepage, the shortest distance path along the surface of a printed circuit board between the solder fillets of the input and output leads must be considered. there are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. creepage and clearance distances will also change depending on factors such as pollution degree and insulation level. solder reflow thermal profile insulation and safety related specifications value parameter symbol 7710 0710 units conditions minimum external air l(i01) 7.1 4.9 mm measured from input terminals to output gap (clearance) terminals, shortest distance through air. minimum external l(i02) 7.4 4.8 mm measured from input terminals to output tracking (creepage) terminals, shortest distance path along body. minimum internal plastic 0.08 0.08 mm insulation thickness between emitter and gap (internal clearance) detector; also known as distance through insulation. tracking resistance cti 3 175 3 175 volts din iec 112/vde 0303 part 1 (comparative tracking index) isolation group iiia iiia material group (din vde 0110, 1/89, table 1) regulatory information the hcpl-x710 have been approved by the following organizations: ul recognized under ul 1577, component recognition program, file e55361. csa approved under csa component acceptance notice #5, file ca 88324. vde (hcpl-7710 option 060) approved according to vde 0884/06.92, file 6591.23-4880-1005. tuv rheinland (hcpl-0710 option 060) approved according to vde 0884/06.92, certificate r9650938. 240 d t = 115?, 0.3?/sec 0 d t = 100?, 1.5?/sec d t = 145?, 1?/sec time ?minutes temperature ?? 220 200 180 160 140 120 100 80 60 40 20 0 260 123 456789101112 (note: use of non-chlorine activated fluxes is recommended.)
5 vde 0884 insulation related characteristics (option 060) hcpl-7710 hcpl-0710 description symbol option 060 option 060 units installation classification per din vde 0110/1.89, table 1 for rated mains voltage 150 v rms i-iv i-iv for rated mains voltage 300 v rms i-iv i-iii for rated mains voltage 450 v rms i-iii climatic classification 55/100/21 55/100/21 pollution degree (din vde 0110/1.89) 2 2 maximum working insulation voltage v iorm 630 560 v peak input to output test voltage, method b? v pr 1181 1050 v peak v iorm x 1.875 = v pr , 100% production test with t m = 1 sec, partial discharge < 5 pc input to output test voltage, method a? v pr 945 840 v peak v iorm x 1.5 = v pr , type and sample test, t m = 60 sec, partial discharge < 5 pc highest allowable overvoltage? v iotm 6000 4000 v peak (transient overvoltage, t ini = 10 sec) safety limiting values (maximum values allowed in the event of a failure, also see thermal derating curve, figure 11.) case temperature t s 175 150 c input current i s,input 230 150 ma output power p s,output 600 600 mw insulation resistance at t s , v 10 = 500 v r io 3 10 9 3 10 9 w ?refer to the front of the optocoupler section of the isolation and control component designers catalog , under product safety regulations section (vde 0884), for a detailed description. note: these optocouplers are suitable for safe electrical isolation only within the safety limit data. maintenance of the safety data shall be ensured by means of protective circuits. note: the surface mount classification is class a in accordance with cecc 00802. absolute maximum ratings parameter symbol min. max. units figure storage temperature t s C55 125 c ambient operating temperature t a C40 +100 c supply voltages v dd1 , v dd2 0 5.5 volts input voltage v i C0.5 v dd1 +0.5 volts output voltage v o C0.5 v dd2 +0.5 volts input current i i C10 +10 ma average output current i o 10 ma lead solder temperature 260 c for 10 sec., 1.6 mm below seating plane solder reflow temperature profile see solder reflow temperature profile section recommended operating conditions parameter symbol min. max. units figure ambient operating temperature t a C40 +100 c supply voltages v dd1 , v dd2 4.5 5.5 v logic high input voltage v ih 2.0 v dd1 v 1, 2 logic low input voltage v il 0.0 0.8 v input signal rise and fall times t r , t f 1.0 ms
6 electrical specifications test conditions that are not specified can be anywhere within the recommended operating range. all typical specifications are at t a = +25 c, v dd1 = v dd2 = +5 v. parameter symbol min. typ. max. units test conditions fig. note dc specifications logic low input i dd1l 6.0 10.0 ma v i = 0 v 1 supply current logic high input i dd1h 1.5 3.0 ma v i = v ddi supply current input supply current i dd1 13.0 ma output supply current i dd2 5.5 11.0 ma input current i i C10 10 m a logic high output v oh 4.4 5.0 v i o = C20 m a, v i = v ih 1, 2 4.0 4.8 i o = -4 ma, v i = v ih logic low output v ol 0 0.1 v i o = 20 m a, v i = v il 0.5 1.0 i o = 4 ma, v i = v il switching propagation delay time t phl 20 40 ns c l = 15 pf 3, 7 2 to logic low output cmos signal levels propagation delay time t plh 23 40 to logic high output pulse width pw 80 3 data rate 12.5 mbd pulse width distortion pwd 3 8 ns 4, 8 4 |t phl - t plh | propagation delay skew t psk 20 5 output rise time t r 9c l = 15 pf 5, 9 (10 - 90%) cmos signal levels output fall time t f 86, (90 - 10%) 10 common mode |cm h | 10 20 kv/ m sv i = v dd1 , v o >6 transient immunity at 0.8 v dd1 , logic high output v cm = 1000 v common mode |cm l |10 20 v i = 0 v, v o > 0.8 v, transient immunity at v cm = 1000 v logic low output input dynamic power c pd1 60 pf 7 dissipation capacitance output dynamic power c pd2 10 dissipation capacitance voltage voltage specifications logic high output voltage logic low output voltage
7 package characteristics parameter symbol min. typ. max. units test conditions fig. note input-output momentary 0710 v iso 2500 vrms rh 50%, 8, 9, withstand voltage t = 1 min., 10 7710 3750 t a = 25 c resistance r i-o 10 12 w v i-o = 500 vdc 8 (input-output) capacitance c i-o 0.6 pf f = 1 mhz (input-output) input capacitance c i 3.0 11 input ic junction-to-case q jci 145 c/w thermocouple thermal resistance 160 located at center output ic junction-to-case q jco 140 thermal resistance 135 package power dissipation p pd 150 mw notes: 1. the led is on when v i is low and off when v i is high. 2. t phl propagation delay is measured from the 50% level on the falling edge of the v i signal to the 50% level of the falling edge of the v o signal. t plh propagation delay is measured from the 50% level on the rising edge of the v i signal to the 50% level of the rising edge of the v o signal. 3. mimimum pulse width is the shortest pulse width at which 10% maximum, pulse width distortion can be guaran- teed. maximum data rate is the inverse of minimum pulse width. operating the hcpl-x710 at data rates above 12.5 mbd is possible provided pwd and data dependent jitter increases and relaxed noise margins are tolerable within the application. for instance, if the maximum allowable variation of bit width is 30%, the maximum data rate becomes 37.5 mbd. please note that hcpl-x710 underside of package performances above 12.5 mbd are not guaranteed by hewlett-packard. 4. pwd is defined as |t phl - t plh |. %pwd (percent pulse width distortion) is equal to the pwd divided by pulse width. 5. t psk is equal to the magnitude of the worst case difference in t phl and/or t plh that will be seen between units at any given temperature within the recommended operating conditions. 6. cm h is the maximum common mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd2 . cm l is the maximum common mode voltage slew rate that can be sustained while maintaining v o < 0.8 v. the common mode voltage slew rates apply to both rising and falling common mode voltage edges. 7. unloaded dynamic power dissipation is calculated as follows: c pd * v dd2 * f + i dd * v dd , where f is switching frequency in mhz. 8. device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together. 9. in accordance with ul1577, each hcpl-0710 is proof tested by applying an insulation test voltage 3 3000 v rms for 1 second (leakage detection current limit, i i-o 5 m a). each hcpl- 7710 is proof tested by applying an insulation test voltage 3 4500 v rms for 1 second (leakage detection current limit, i i-o 5 m a). 10. the input-output momentary with- stand voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. for the continuous voltage rating refer to your equipment level safety specification or hp application note 1074 entitled optocoupler input-output endurance voltage. 11. c i is the capacitance measured at pin 2 (v i ). figure 1. typical output voltage vs. input voltage. figure 2. typical input voltage switching threshold vs. input supply voltage. figure 3. typical propagation delays vs. temperature. v o (v) 0 0 v i (v) 5 4 1 4 123 5 3 2 0 ? 25 ? 85 ? v ith (v) 4.5 1.6 v dd1 (v) 5.5 2.1 1.7 5.25 4.75 5 2.2 2.0 1.8 1.9 0 ? 25 ? 85 ? t plh , t phl (ns) 0 15 t a (c) 80 27 17 60 20 30 29 25 19 21 10 40 50 70 23 t plh t phl -7710 -0710 -7710 -0710
8 figure 10. typical fall time vs. load capacitance. figure 4. typical pulse width distortion vs. temperature. figure 5. typical rise time vs. temperature. figure 6. typical fall time vs. temperature. figure 9. typical rise time vs. load capacitance. figure 11. thermal derating curve, dependence of safety limiting value with case temperature per vde 0884. pwd (ns) 0 0 t a (c) 80 3 60 20 4 1 40 2 t r (ns) 0 8 t a (c) 80 10 60 20 11 9 40 t f (ns) 0 2 t a (c) 80 6 60 20 7 3 40 5 4 t r (ns) 0 1 c i (pf) 35 19 25 21 5 15 11 10 52030 7 15 17 13 9 3 fall time (ns) 0 0 c i (pf) 35 9 25 10 2 15 5 10 52030 3 7 8 6 4 1 output power ?p s , input current ?i s 0 0 t a ?case temperature ?? 200 50 400 125 25 75 100 150 600 800 200 100 300 500 700 175 (230) p s (mw) i s (ma) standard 8 pin dip product output power ?p s , input current ?i s 0 0 t a ?case temperature ?? 200 50 400 125 25 75 100 150 600 800 200 100 300 500 700 175 (150) p s (mw) i s (ma) surface mount so8 product t plh , t phl (ns) 15 15 c i (pf) 50 27 40 29 17 30 23 21 25 20 35 45 19 25 t plh t phl pwd (ns) 15 0 c i (pf) 50 5 40 6 1 30 3 25 20 35 45 2 4 figure 7. typical propagation delays vs. output load capacitance. figure 8. typical pulse width distortion vs. output load capacitance.
9 application information bypassing and pc board layout the hcpl-x710 optocouplers are extremely easy to use. no external interface circuitry is required because the hcpl-x710 use high-speed cmos ic technology allowing cmos logic to be connected directly to the inputs and outputs. as shown in figure 12, the only external components required for proper operation are two bypass capacitors. capacitor values should be between 0.01 m f and 0.1 m f. for each capacitor, the total lead length between both ends of the capacitor and the power-supply pins should not exceed 20 mm. figure 13 illustrates the recommended printed circuit board layout for the hpcl-x710. figure 12. recommended printed circuit board layout. figure 13. recommended printed circuit board layout. v dd2 c1 c2 710 yww v o gnd 2 v dd1 v i gnd 1 c1, c2 = 0.01 ? to 0.1 ? 7 5 6 8 2 3 4 1 gnd 2 c1 c2 nc v dd2 nc v o v dd1 v i 710 yww c1, c2 = 0.01 ? to 0.1 ? gnd 1 propagation delay, pulse- width distortion and propagation delay skew propagation delay is a figure of merit which describes how quickly a logic signal propagates through a system. the propaga- tion delay from low to high (t plh ) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. similarly, the propagation delay from high to low (t phl ) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low. see figure 14. figure 14. input t plh t phl output v i v o 10% 90% 90% 10% v oh v ol 0 v 50% 5 v cmos 2.5 v cmos
10 figure 15. propagation delay skew waveform. figure 16. parallel data transmission example. propagation delay skew repre- sents the uncertainty of where an edge might be after being sent through an optocoupler. figure 16 shows that there will be uncertainty in both the data and clock lines. it is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. from these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice t psk . a cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. the hcpl-x710 optocouplers offer the advantage of guaranteed specifications for propagation delays, pulse-width distortion, and propagation delay skew over the recommended temperature and power supply ranges. pulse-width distortion (pwd) is the difference between t phl and t plh and often determines the maximum data rate capability of a transmission system. pwd can be expressed in percent by dividing the pwd (in ns) by the minimum pulse width (in ns) being trans- mitted. typically, pwd on the order of 20 - 30% of the minimum pulse width is tolerable. the pwd specification for the hcpl-x710 is 8 ns (10%) maximum across recommended operating condi- tions. 10% maximum is dictated by the most stringent of the three fieldbus standards, profibus. propagation delay skew, t psk , is an important parameter to con- sider in parallel data applications where synchronization of signals on parallel data lines is a concern. if the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. if this difference in propagation delay is large enough it will determine the maximum rate at which parallel data can be sent through the optocouplers. propagation delay skew is defined as the difference between the minimum and maximum propa- gation delays, either t plh or t phl , for any given group of optocoup- lers which are operating under the same conditions (i.e., the same drive current, supply volt- age, output load, and operating temperature). as illustrated in figure 15, if the inputs of a group of optocouplers are switched either on or off at the same time, t psk is the difference between the shortest propagation delay, either t plh or t phl , and the longest propagation delay, either t plh or t phl . as mentioned earlier, t psk can determine the maximum parallel data transmission rate. figure 16 is the timing diagram of a typical parallel data application with both the clock and data lines being sent through the optocouplers. the figure shows data and clock signals at the inputs and outputs of the optocouplers. in this case the data is assumed to be clocked off of the rising edge of the clock. 50% 50% t psk v i v o v i v o 2.5 v, cmos 2.5 v, cmos data inputs clock data outputs clock t psk t psk
11 optical isolation for field bus networks to recognize the full benefits of these networks, each recom- mends providing galvanic isolation using agilent optocouplers. since network communication is bi-directional (involving receiving data from and transmitting data onto the network), two agilent optocouplers are needed. by providing galvanic isolation, data integrity is retained via noise reduction and the elimination of figure 17. typical field bus communication physical model. false signals. in addition, the network receives maximum protection from power system faults and ground loops. within an isolated node , such as the devicenet node shown in figure 18, some of the nodes components are referenced to a ground other than v- of the network. these components could include such things as devices with serial ports, parallel ports, rs232 and rs485 type ports. as shown in figure 18, power from the network is used only for the transceiver and input (network) side of the optocouplers. isolation of nodes connected to any of the three types of digital field bus networks is best achieved by using the hcpl-x710 optocouplers. for each network, the hcpl-x710 satisify the critical propagation delay and pulse width distortion require- ments over the temperature range of 0 c to +85 c, and power supply voltage range of 4.5 v to 5.5 v. digital field bus communication networks to date, despite its many draw- backs, the 4 - 20 ma analog current loop has been the most widely accepted standard for implementing process control systems. in todays manufacturing environment, however, automated systems are expected to help manage the process, not merely monitor it. with the advent of digital field bus communication networks such as devicenet, profibus, and smart distributed systems (sds), gone are the days of constrained information. controllers can now receive multiple readings from field devices (sensors, actuators, etc.) in addition to diagnostic information. the physical model for each of these digital field bus communica- tion networks is very similar as shown in figure 17. each includes one or more buses, an interface unit, optical isolation, transceiver, and sensing and/or actuating devices. controller transceiver optical isolation bus interface transceiver optical isolation bus interface transceiver optical isolation bus interface transceiver optical isolation bus interface transceiver optical isolation bus interface field bus xxxxxx yyy sensor device configuration motor starter motor controller
12 implementing devicenet and sds with the hcpl-x710 with transmission rates up to 1 mbit/s, both devicenet and sds are based upon the same broadcast-oriented, communica- tions protocol the controller area network (can). three types of isolated nodes are recommended for use on these networks: isolated node powered figure 18. typical devicenet node. by the network (figure 19), isolated node with transceiver powered by the network (figure 20), and isolated node providing power to the network (figure 21). isolated node powered by the network this type of node is very flexible and as can be seen in figure 19, is regarded as isolated because not all of its components have the figure 19. isolated node powered by the network. same ground reference. yet, all components are still powered by the network. this node contains two regulators: one is isolated and powers the can controller, node- specific application and isolated (node) side of the two optocoup- lers while the other is non- isolated. the non-isolated regulator supplies the transceiver and the non-isolated (network) half of the two optocouplers. node/app specific up/can hcpl x710 hcpl x710 transceiver local node supply 5 v reg. network power supply v+ (signal) v?(signal) v+ (power) v?(power) galvanic isolation boundary ac line drain/shield signal power node/app specific up/can hcpl x710 hcpl x710 transceiver reg. v+ (signal) v?(signal) v+ (power) v?(power) galvanic isolation boundary drain/shield signal power isolated switching power supply network power supply
13 figure 20. isolated node with transceiver powered by the network. isolated node with transceiver powered by the network figure 20 shows a node powered by both the network and another source. in this case, the trans- ceiver and isolated (network) side of the two optocouplers are powered by the network. the rest of the node is powered by the ac line which is very beneficial when an application requires a significant amount of power. this method is also desirable as it does not heavily load the network. more importantly, the unique dual-inverting design of the hcpl-x710 ensure the network will not lock-up if either ac line power to the node is lost or the node powered-off. specifically, when input power (v dd1 ) to the hcpl-x710 located in the transmit path is eliminated, a recessive bus state is ensured as the hcpl-x710 output voltage (v o ) go high. *bus v+ sensing it is suggested that the bus v+ sense block shown in figure 20 be implemented. a locally powered node with an un- powered isolated physical layer will accumulate errors and become bus-off if it attempts to transmit. the bus v+ sense signal would be used to change the boi attribute of the devicenet object to the auto-reset (01) value. refer to volume 1, section 5.5.3. this would cause the node to continually reset until bus power was detected. once power was detected, the boi attribute would be returned to the hold in bus-off (00) value. the boi attribute should not be left in the auto-reset (01) value since this defeats the jabber protection capability of the can error confinement. any inexpensive low frequency optical isolator can be used to implement this feature. node/app specific up/can hcpl x710 hcpl x710 transceiver non iso 5 v reg. network power supply v+ (signal) v?(signal) v+ (power) v?(power) galvanic isolation boundary ac line drain/shield signal power *hcpl x710 * optional for bus v + sense
14 figure 21. isolated node providing power to the network. isolated node providing power to the network figure 21 shows a node providing power to the network. the ac line powers a regulator which provides five (5) volts locally. the ac line also powers a 24 volt isolated supply, which powers the network, and another five-volt regulator, which, in turn, powers the transceiver and isolated (network) side of the two optocouplers. this method is recommended when there are a limited number of devices on the network that dont require much power, thus eliminating the need for separate power supplies. more importantly, the unique dual-inverting design of the hcpl-x710 ensure the network will not lock-up if either ac line power to the node is lost or the node powered-off. specifically, when input power (v dd1 ) to the hcpl-x710 located in the transmit path is eliminated, a recessive bus state is ensured as the hcpl-x710 output voltage (v o ) go high. node/app specific up/can hcpl x710 hcpl x710 transceiver 5 v reg. v+ (signal) v?(signal) v+ (power) v?(power) galvanic isolation boundary ac line drain/shield signal power isolated switching power supply 5 v reg. devicenet node
15 power supplies and bypassing the recommended devicenet application circuit is shown in figure 22. since the hcpl-x710 are fully compatible with cmos logic level signals, the optocoup- ler is connected directly to the figure 22. recommended devicenet application circuit. implementing profibus with the hcpl-x710 an acronym for process fieldbus, profibus is essentially a twisted-pair serial link very similar to rs-485 capable of achieving high-speed communi- cation up to 12 mbd. as shown in figure 23, a profibus control- ler (pbc) establishes the connec- tion of a field automation unit (control or central processing station) or a field device to the transmission medium. the pbc consists of the line transceiver, optical isolation, frame character transmitter/receiver (uart), and the fdl/app processor with the interface to the profibus user. can transceiver. two bypass capacitors (with values between 0.01 and 0.1 m f) are required and should be located as close as possible to the input and output power-supply pins of the hcpl- x710. for each capacitor, the figure 23. profibus controller (pbc). profibus user: control station (central processing) or field device user interface fdl/app processor transceiver optical isolation uart pbc medium total lead length between both ends of the capacitor and the power supply pins should not exceed 20 mm. the bypass capac- itors are required because of the high-speed digital nature of the signals inside the optocoupler. 8 7 6 1 3 5 2 4 v dd1 v in gnd 1 v dd2 v o gnd 2 hcpl-x710 4 3 2 5 7 1 6 8 gnd 2 v o v dd2 gnd 1 v in v dd1 hcpl-x710 gnd iso 5 v iso 5 v 0.01 ? rx0 0.01 ? tx0 0.01 ? 0.01 ? txd canh ref rxd 82c250 v cc gnd rs canl c4 0.01 ? + vref linear or switching regulator 5 v 5 v ++ r1 1 m c1 0.01 ? 500 v d1 30 v 5 v+ 4 can+ 3 shield 2 can 1 v galvanic isolation boundary
figure 24. recommended profibus application circuit. 1 2 3 8 6 4 7 5 v dd2 v o gnd 2 v dd1 v in gnd 1 hcpl-x710 8 7 6 1 3 5 2 4 v dd1 v in gnd 1 v dd2 v o gnd 2 hcpl-x710 5 v 0.01 ? 0.01 ? 0.01 ? 0.01 ? r a sn75176b v cc gnd de b 0.01 ? iso 5 v 1 m 0.01 ? + galvanic isolation boundary 5 v iso 5 v re d 1 4 3 2 rx iso 5 v tx 8 7 6 1 3 5 2 4 anode v cc v o gnd 5 v 0.01 ? iso 5 v tx enable cathode v e 680 w hcpl-061n 1, 0 k w 5 7 6 8 rt shield power supplies and bypassing the recommended profibus application circuit is shown in figure 24. since the hcpl-x710 are fully compatible with cmos logic level signals, the optocoupler is connected directly to the transceiver. two bypass capacitors (with values between 0.01 and 0.1 m f) are required and should be located as close as possible to the input and output power-supply pins of the hcpl-x710. for each capacitor, the total lead length between both ends of the capacitor and the power supply pins should not exceed 20 mm. the bypass capacitors are required because of the high-speed digital nature of the signals inside the optocoupler. being very similar to multi-station rs485 systems, the hcpl-061n optocoupler provides a transmit disable function which is necessary to make the bus free after each master/slave transmission cycle. specifically, the hcpl-061n disables the transmitter of the line driver by putting it into a high state mode. in addition, the hcpl-061n switches the rx/tx driver ic into the listen mode. the hcpl-061n offers hcmos compatibility and the high cmr performance (1 kv/ m s at v cm = 1000 v) essential in industrial communication interfaces. www.semiconductor.agilent.com data subject to change. copyright ? 1999 agilent technologies obsoletes 5968-2818e 5968-7458e (11/99)

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